In a conventional cathode ray tube (CRT) display device, it is generally known that it is necessary to repeatedly refresh the screen on the CRT, normally on the order of 50-60 times per second, in order to maintain the displayed state and in the manner wherein a controller sequentially reads out all addresses in a refresh memory. In addition, it is also necessary to access the refresh memory from a central processing unit (CPU) for any modification of the screen-displayed content and for other purposes. However, competitive accessing the refresh memory from or by the central processing unit and the controller causes a flash or like flicker to be generated or present on a portion of the screen.
In order to avoid this flashing or flickering on the screen, an MC 6800 series synchronous bus system, as manufactured by Motorola Corporation, Schaumberg, Ill., and including a system clock, has been developed or contrived so as to access the memory from the central processing unit during the time when the system clock is at a high level, and to access the memory from the controller during the time when the system clock is at a low level. On the other hand, in the case of an asynchronous bus system having no system clock, such as the Z-80 type, as manufactured by Zilog Corporation, Cupertino, Calif., the memory is preferably accessed from the central processing unit during the horizontal or during the vertical blanking periods. However, according to this latter method, accessing from the central processing unit is limited to short-time blanking periods, and it is seen that a draw-back or disadvantage of such method is that the processing speed of the central processing unit is reduced.
In the prior art and as a solution to these draw-backs, there has been proposed a technique described in Japanese Laid-Open Patent Specification No. 66,989/83 wherein reference clocks in the central processing unit and the cathode ray tube controller are synchronized in alternating manner so as to permit the memory access from the CPU only during the time when the reference clock of the CRT controller is at a low level, and to permit the memory access from the CRT controller only during the time when the reference clock of the controller is at a high level, thereby avoiding the competitive accessing from or by the CPU and the CRT controller. However, in this arrangement, the reference clock in the CRT controller is divided into halves so as to assign individual halved periods as access time of the CPU and the CRT controller so that as to refresh memory access and its associated peripheral circuit elements, it was necessary to use high speed elements capable of operating at least in a period which is one-half the conventional period. Further, the reference clocks of the CPU and the CRT controller have been controlled so as to operate in synchronized manner in order to avoid such competitive accessing with the result that the structure of the control unit and the peripheral units was complicated or complex in nature.
Further documentation in the field of video display systems includes U.S. Pat. No. 3,753,240, issued to R. L. Merwin on Aug. 14, 1973, which discloses a data entry and retrieval composite display system wherein electronic means transforms film, microfiche, transparent slides, and video tape data into a video signal and combines such signal with computer originated data which is reduced to a video signal and then displays the combined signals as a composite video display.
U.S. Pat. No. 4,070,664, issued to M. Abe on Jan. 24, 1978, discloses a display system having separated display periods and key input periods wherein a computing module generates a repeating sequential series of first pulses and a group of second pulses for energizing a display device. During a first period of predetermined time interval, the display device is driven by first and second pulses while during a second period of the time interval, the display device is not driven but the timing pulses are coupled to the computing module.
U.S. Pat. No. 4,093,996, issued to W. J. Hogan et al. on June 6, 1978, discloses a cursor circuit for a television display having an intermediate buffer and a refresh buffer. The cursor circuit secures the identity of the encoded symbol in the intermediate buffer during the first display frame and this identity is the address of the symbol as stored in the refresh buffer. This identity is made available for accessing the refresh buffer during a second display frame.
U.S. Pat. No. 4,127,851, issued to A. P. Middel on Nov. 28, 1978, discloses a device for displaying a number of lines of characters and has a circulating store for one line of characters connected to the output of a buffer store for the entire image information. An output of the circulating store is input to the buffer store and is switched from its output to the output of the circulating store so that information in the buffer store is shifted.
U.S. Pat. No. 4,223,353, issued to John T. Keller on Sept. 16, 1980, discloses a video display device having a memory for storing intensity values and connected with the memory is a persistor which decreases the intensity values as a function of time. Also connected with the memory is an input for increasing specific intensity values in response to receipt of input data corresponding to a particular display pixel.
U.S. Pat. No. 4,236,153, issued to W. Aling on Nov. 25, 1980, discloses a low-noise character element display device wherein the display elements are periodically and gradually switched on and off and the information is changed or displaced at instants that the display elements are switched off.
U.S. Pat. No. 4,237,543, issued to Y. Nishio et al. on Dec. 2, 1980, discloses a microprocessor controlled display system having a data control unit including a microprocessor and an associated memory, a refresh memory unit connected to the data control unit through an address bus and a data bus, and a video control unit for accessing display data stored in the refresh memory unit by a timing control unit to produce a video signal. The refresh memory unit comprises memories sectioned by byte, an I/O controller which receives a read/write control signal to indicate whether the access by the data control unit is read access or write access, and an access memory specifying signal to indicate one or two byte memory access to produce an I/O control signal, and a memory controller responsive to the I/O signal to control data access to the memories.
U.S. Pat. No. 4,278,974, issued to K. Kondo on July 14, 1981, discloses a driving system for a matrix display device having X and Y electrodes with a timing signal generator for controlling the X scanning signals, and a display signal converter for converting display information into a portion of signals for display. A memory device stores the signals for display and the drive to the Y electrodes is inhibited while information is being stored in the memory.
U.S. Pat. No. 4,356,482, issued to T. Oguchi on Oct. 26, 1982, discloses an image pattern control system having a dynamic memory which operates during a first period to read and rewrite the contents of memory according to address data sent from an address register and to refresh stored data according to the output of a refresh counter during a second period. The first and second periods are switched according to the output of a zoom hold register.
U.S. Pat. No. 4,359,730, issued to A. Kunikane et al. on Nov. 16, 1982, discloses an alphanumeric information display system controlled by a microprocessor wherein first and second memory means are accessed in pre-determined periods of time to provide a display shifted by a number of characters on a word-for-word basis.
U.S. Pat. No. 4,379,293, issued to C. Boisvert et al. on Apr. 5, 1983, discloses a CRT controller connected to a processor and having a refresh address generator to refresh display on the CRT, an update address generator to update information in refresh memory, and a control circuit for connecting the update address generator and the refresh address generator to refresh the memory so that only one of the generators has control of the refresh memory at a time.
U.S. Pat. No. 4,399,435, issued to K. Urabe on Aug. 16, 1983, discloses a digital data display apparatus wherein data are stored in a refresh memory and displayed on a CRT and the apparatus includes a first and a second buffer memory so that data read out from the refresh memory can be stored by odd and even rows. When display data in the first or second memory are displayed in odd or even rows on the display screen, the horizontal period of that row is used to read out display data for the other row from the refresh memory, and store the same in the second or first buffer memory. The display data are alternately stored in and read-out from the first and second buffer memories so that all data can be displayed over the entire area of the display screen.
U.S. Pat. No. 4,408,197, issued to S. Komatsu et al. on Oct. 4, 1983, discloses a pattern display apparatus for use with a CRT and having a composite video signal synthesizer, a memory for storing pattern data, a mode setting circuit for the memory, a data selection signal generator, and a raster line number signal generator. The memory stores data for simple patterns such as alphabetical letters, and those for relatively complicated patterns such as Chinese characters in individual areas in the memory addresses are identified by a combination of data selection and raster line number signals supplied to the memory from the respective generators.
U.S. Pat. No. 4,418,343, issued to J. L. Ryan et al. on Nov. 29, 1983, discloses a CRT refresh memory system which has a CPU, a memory unit, a video control system, a timing control system, and a communication system each connected to the others by common system address, data, and control buses. The accessing of a display memory by both the CPU and the video control system over the common address bus is accommodated without the need for multiplexing the system address bus or compromising either the system data transfer rates or CPU instruction execution speeds.
And, U.S. Pat. No. 4,434,472, issued to L. Kachun on Feb. 28, 1984, discloses a terminal system including microprocessor controlled line refresh apparatus having addressable screen memory means for storing display data, temporary storage means for address data, incrementing means coupled to the memory means and supplied with display data address from the temporary storage, and microprocessor means for supplying data address to the temporary storage on a line-by-line basis in real time so that line refresh data supplied to the character generator may be varied by real time manipulation of line address data by the microprocessor means.